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2- /4 - /8 - channel, 1 msps, ultralow power, 12 - bit adc in 16 - /20 - /24 - lead tssop data sheet ad7091r-2 /ad7091r-4 /ad7091r-8 features fast throughput rate: 1 msps specified for v dd of 2.7 v to 5.25 v ultra l ow power : 467 a typical at 3 v and 1 msps on - chip accurate 2.5 v r eference, 5 ppm/ c typical drift 2 , 4, and 8 single - ended analog input channels programmable channel sequencer a lert f unction available in 4 - and 8 - channel versions b usy indication available in 4 - and 8 - channel versions gp ox pins available in 4 - and 8 - channel versions wide input bandwidth 70 db signal - to - noise ratio ( snr ) typical at input frequency of 10 khz flexible power/throughput rate management no pipeline delays high speed s erial interface spi/qspi?/ microwire? /dsp compatible daisy - chain mode power - down m ode 55 0 na typical at v dd = 5.25 v 435 na typical at v dd = 3 v 16 - lead , 20 - lead , and 24 - lead ts sop package s temperature range: ? 40 c to +125c applications battery - powered systems personal digital assistants medical i nstruments mobile c ommunications instrumentation and control systems data acquisition syste ms optical s ensors diagnostic/monitoring functions general description the ad7091r -2 / ad7091r -4 / ad7091r -8 family is a multichannel 12- bit, ultralow power, successive approximation analog - to - converter (adc) that is available in two, four , or eight analog input channel options . the ad7091r -2 / ad7091r -4 / ad7091r -8 operate from a single 2.7 v to 5.25 v power supply and is capable of achieving a sampling rate of 1 msps. the ad7091r -2 / ad7091r -4 / ad7091r -8 contain a wide bandwidth track - and - hold amplifier that can operate at input frequencies in excess of 1.5 mhz . the ad7091r -2 / a d7091r -4 / ad7091r -8 also feature an on - chip conversion clock, an on - chip accurate 2.5 v reference, and a high speed serial interface . functional block dia gram f igure 1. t he ad7091r -2 / ad7091r -4 / ad7091r -8 family offers up to eight single- ended analog input channels with a channel sequencer that allows a preprogrammed selection of channels to be converted sequentially. the ad7091r -2 / ad7091r -4 / ad7091r -8 ha ve a serial port interface ( spi ) tha t allows data to be read after the conversion while achieving a 1 msps throughput rate. the conversion process and data acquisition are controlled using the convst pin. the ad7091r -2 / ad7091r -4 / ad7091r -8 use advanced design techniques to achieve ultralow power dissipation at high throughput rates. they also feature flexible power management options. an on - chip configuration register allows the user to set up different operating conditions. these include p ower management, alert functionality , busy indication, channel sequencing , and general - purpose output pins. the mux out and adc in pins allow signal conditioning of the multiplexer output prior to acquisition by the adc . gnd regcap v dd ad7091r-8 ref in / ref out mux out adc in gnd t/h i/p mux channel sequencer control logic and registers 12-bit successive approximation adc 2.5v vref on-chip osc gpo 1 alert/ busy/ gpo 0 sdo sdi v drive convst reset sclk cs 10891-001 v in 0 v in 1 v in 2 v in 3 v in 7 v in 6 v in 5 v in 4 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliab le. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. o ne technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com
important links for the ad7091r-2_7091r-4_7091r-8 * last content update 02/19/2014 10:48 am similar products & parametric selection tables find similar products by operating parameters documentation ug-633: evaluating the ad7091r-2/ad7091r-4/ad7091r-8 12-bit monitor and control system suggested companion products recommended driver amplifiers for the ad7091r-2/ ad7091r-4/ ad7091r-8 for low frequency and low bias current, we recommend the ada4627-1, ada4637-1 or the ad8610 . for precision, low power, rail-to-rail output, we recommend the ada4841-1, ada4896-2 or the ad8031 . for high frequency, low noise, low distortion, we recommend the ada4899-1, ada4897-1 or the ad8021 . for additional driver amplifier selections , we recommend selecting the product category and filtering on our parametric search tables. recommended external references for the ad7091r-2/ ad7091r-4/ ad7091r-8 for a 3v, low power, low noise, we recommend the adr4530 or the ref193 . for a 5v, low power, low noise, we recommend the adr4550 or the ref195 . for additional voltage reference selections , we recommend filtering on our parametric search tables. recommended power solutions for the ad7091r-2/ ad7091r-4/ ad7091r-8 for selecting voltage regulator products, use adisimpower . for selecting supervisor products, use the supervisor parametric search . evaluation kits & symbols & footprints view the evaluation boards and kits page for documentation and purchasing symbols and footprints for the ad7091r-2 symbols and footprints for the ad7091r-4 symbols and footprints for the ad7091r-8 design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data package information sample & buy ad7091r-2 ad7091r-4 ad7091r-8 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifi cations .................................................................. 5 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ........................................... 12 terminology .................................................................................... 17 theory of operation ...................................................................... 18 circuit information .................................................................... 18 converte r operation .................................................................. 18 adc transfer function ............................................................. 18 reference ..................................................................................... 18 typical connection diagram .................................................... 19 an alog input ............................................................................... 19 registers ........................................................................................... 21 addressing registers .................................................................. 21 conversion result register ....................................................... 22 channel register ........................................................................ 23 configuratio n register .............................................................. 24 alert indication register ........................................................... 26 channel x low limit register .................................................. 28 channel x high limit register ................................................. 28 channel x hysteresis register .................................................. 28 serial interface ................................................................................ 29 reading conversion result ....................................................... 29 writing data to the registers ................................................... 29 reading data from the registers .............................................. 29 modes of operation ....................................................................... 31 normal mode .............................................................................. 31 power - down mode .................................................................... 31 a lert ( ad7091r - 4 and ad7091r - 8 only) .......................... 32 busy ( ad7091r - 4 and ad7091r - 8 only) ............................. 32 channel sequencer .................................................................... 33 daisy chain ................................................................................. 34 outline dimensio ns ....................................................................... 36 ordering guide .......................................................................... 37 revision history 1 2 /13 revision 0: initial version rev. 0 | page 2 of 40
data sheet ad7091r- 2/ ad7091r - 4/ad7091r - 8 specifications v dd = 2.7 v to 5.25 v, v drive = 1.8 v to 5.25 v, v ref = 2.5 v internal re ference, f sample = 1 msps, f sclk = 5 0 mhz, t a = t min to t max , unless otherwise noted . table 1 . parameter test conditions/comments min typ max unit dynamic performance f in = 10 khz sine wave signal - to - noise ratio (snr) 66.5 70 db signal - to - noise + distortion (sinad) 65.5 69 db total harmonic distortion (thd) ? 8 0 db spurious - free dynamic range (sfdr) f in = 1 khz sine wave ?81 db channel - to - channel isolation ?95 db aperture delay 5 ns aperture jitter 40 ps full power bandwidth at ?3 db 1.5 mhz at ?0.1 db 1.2 mhz dc accuracy resolution 12 bits integral nonlinearity (inl) v dd 3.0 v ? 1 0. 7 + 1 lsb v dd 2.7 v ?1.25 0.8 + 1 .25 lsb differential nonlinearity (dnl) guaranteed no missing codes to 12 bits ?0.9 0.3 + 0.9 lsb offset error t a = 25c ?1.5 0.2 +1.5 mv offset error matching t a = 25c ?1.5 0.2 +1.5 mv offset error drift 2 ppm/c gain error t a = 25c ?0.1 0.0 +0.1 % fs gain error matching t a = 25c ?0.1 0.0 +0.1 % fs gain error drift 2 ppm/c analog input input voltage range 0 v ref v dc leakage current ?1 + 1 a input capacitance 1 during acquisition phase 10 pf outside acquisition phase 1 .5 pf voltage reference input/output ref out 2 internal reference o utput , t a = 25c 2.49 2.5 2.5 1 v ref in 2 external reference input 1.0 v dd v drift 5 ppm/c power - on time c ref = 2.2 f 50 ms logic inputs input high voltage (v ih ) 0.7 v drive v input low voltage (v il ) 0.3 v drive v input current (i in ) typically 10 na, v in = 0 v or v drive ?1 +1 a logic outputs output high voltage (v oh ) i source = 200 a v drive ? 0.2 v output low voltage (v ol ) i sink = 200 a 0.4 v floating state leakage current ?1 +1 a output coding straight (natural) binary conversion rate conversion time 600 ns transient response full - scale step input 400 ns throughput rate 1 msps rev. 0 | page 3 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet parameter test conditions/comments min typ max unit power requirements v dd 2.7 5.25 v v drive specified performance 2.7 5.25 v v drive range 3 functional 1.8 5.25 v i dd v in = 0 v normal mode static 4 v dd = 5.25 v 22 50 a v dd = 3 v 21.6 46 a normal mode operational v dd = 5.25 v, f sample = 1 msps 5 00 570 a v dd = 3 v, f sample = 1 msps 4 50 530 a power - down mode v dd = 5.25 v 0. 550 17 a v dd = 5.25 v, t a = ?40c to +85c 0. 550 6 a v dd = 3 v 0.435 15 a i drive v in = 0 v normal mode static 5 v drive = 5.25 v 2 4 a v drive = 3 v 1 3.5 a normal mode operational v drive = 5.25 v, f sample = 1 msps 30 70 a v drive = 3 v, f sample = 1 msps 1 7 15 a power - down mode v drive = 5.25 v 1 a v drive = 3 v 1 a total power dissipation 6 v in = 0 v normal mode static v dd = v drive = 5.25 v 0. 1 30 0.2 90 mw v dd = v drive = 3 v 0.070 0.149 mw normal mode operational v dd = v drive = 5.25 v, f sample = 1 msps 2. 8 3 .4 mw v dd = v drive = 3 v, f sample = 1 msps 1.4 1.7 mw power - down mode v dd = 5.25 v 3 95 w v dd = 5.25 v, t a = ?40c to +85c 3 33 w v dd = v drive = 3 v 1.4 50 w 1 sample tested during initial release to ensure compliance. 2 when referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is releva nt to the specification is listed. for full pin names of multifunction pins, refer to the pin configurations and function descriptions section. 3 device is functional and meets dynamic performance/dc accuracy specifications with v drive down to 1.8 v, but the device is not capable of achieving a throughput of 1 msps. 4 sclk operates in burst mode , and cs idl es high. with a free running sclk and cs pulled low, the i dd static current is increased by 30 a typical at v dd = 5.25 v. 5 sclk operates in burst mode , and cs is idl es high. with a free running sclk and cs pulled low, the i drive static current is increased by 32 a typical at v drive = 5.25 v. 6 total power dissipation includes contributions from v dd , v drive , and ref in (see note 2). rev. 0 | page 4 of 40
data sheet ad7091r- 2/ ad7091r - 4/ad7091r - 8 timing specification s v dd = 2.7 v to 5.25 v, v drive = 1.8 v to 5.25 v, t a = t min to t max , unless otherwise noted. table 2 . parameter symbol min typ max unit conversion time: c o nvst falling edge to data available t conv ert 600 ns acquisition time t acq 400 ns time between conversions (normal mode) t cyc 1000 ns convst p ulse width t cnv pw 10 500 ns sc l k period ( normal mode) t scl k ns v drive above 2.7 v 16 ns v drive above 1.8 v 2 2 ns sclk period (chain mode) t sclk ns v drive above 2.7 v 20 ns v drive above 1.8 v 25 ns sclk low time t sclkl 6 ns sclk high time t sclkh 6 ns sclk falling edge to data remains valid t hsdo 5 ns sclk falling edge to data valid delay t dsdo v drive above 4.5 v 12 ns v drive above 3.3 v 13 ns v drive above 2.7 v 14 ns v drive above 1.8 v 20 ns end of conversion to cs falling edge t eoccsl 5 ns cs low to sdo enabled t en 5 ns cs high or last sc l k falling edge to sdo high impedance t dis 5 ns sdi data set u p time prior to sclk rising edge t ssdisc l k 5 ns sdi data hold time after sclk rising edge t hsdisc l k 2 ns last sclk falling edge to next convst falling edge t quiet 50 ns figure 2 . load circuit for digital interface timing figure 3 . voltage levels for timing 500a i ol 500a i oh 1.4v to sdo c l 20pf 10891-138 x % v drive v i h 2 v i l 2 v i l 2 v i h 2 1 f o r 3 . 0 v , x = 90 and y = 10 ; f o r > 3 . 0 v , x = 70 and y = 30 . 2 m i n i m u m v i h and m a x i m u m v i l u se d . see spe c i f i ca t io n s f o r d igi t a l i n p u t s p ara me t e r i n t ab l e 2. 10891-139 t delay t delay notes y % v drive v drive v drive rev. 0 | page 5 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet timing diagram figure 4 . serial port timing tristate tristate cs sclk 1 5 15 2 3 4 ch_id0 alert db9 db1 db0 t sclkh db11 db10 sdo convst eoc 7 t eoccsl t quiet t cnvpw t convert 16 6 add3 add2 add1 db1 db0 add0 rw sdi add4 ch_id2 db9 t en t sclkl t dis t dsdo t ssdisclk 10891-002 ch_id1 t hsdisclk t acq t cyc t hsdo t sclk rev. 0 | page 6 of 40
data sheet ad7091r-2/ad7091r-4/ad7091r-8 absolute maximum rat ings t a = 25c, unless otherwise noted . table 3. parameter rating v dd to gnd ?0.3 v to +7 v v drive to gnd ?0.3 v to +7 v analog input voltage to gnd ?0.3 v to v ref + 0.3 v digital input 1 voltage to gnd ?0.3 v to v drive + 0.3 v digital output 2 voltage to gnd ?0.3 v to v drive + 0.3 v input current to any pin except supplies 3 10 ma operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c esd human body model ( hbm ) 1.5 kv field induced charged device model ( ficdm ) 500 v 1 the digital input pins include the following: reset , convst , sdi, sclk, and cs . 2 the digital output pins include the following: sdo, gpo 1 , and alert/busy/gpo 0 . 3 transient currents of up to 100 ma do not cause scr latch - up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resistance package type ja jc unit 24 - lead tssop 73.54 14.94 c/w 20 - lead tssop 84.29 18.43 c/w 16 - lead tssop 106.03 28.31 c/w esd caution rev. 0 | page 7 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet pin configuration s and function descrip tions figure 5. 2 - channel pin configuration table 5 . 2 - channel pin function descriptions pin no. mnemonic description 1 cs chip select input. when cs is held low, the serial bus enables and cs frames the output data on the spi. 2 reset reset. logic input. 3 v dd power supply input. the v dd range is from 2.7 v to 5.25 v. decouple this supply pin to gnd. 4 regcap decoupling capacitor pin for voltage output from internal regulator. decouple this output pin separately to gnd using a 2.2 f capacitor. 5 ref in /ref out voltage reference output, 2.5 v. decouple this pin to gnd. t he t ypical recommended decoupling capacitor value is 2.2 f. the user can either access the internal 2.5 v reference or overdrive the internal reference with the voltage applied to this pin. the reference voltage range for an externally applied reference is 1.0 v to v dd . 6, 11 gnd chip ground. these pins are the ground reference point for all circuitry on the ad7091r -2 . 7 mux out multiplexer output. the output of the multiplexer appears at this pin. if no external filtering or buffering is required, tie this pin directly to the adc in pin; otherwise, tie the output of the conditioning network to the adc in pin. 8 v in 0 analog input 0 . single - ended analog input. the analog input range is 0 v to v ref . 9 v in 1 analog input 1. single - ended analog input. the analog input range is 0 v to v ref . 10 adc in adc input. this pin allows access to the on - chip track - and - hold. if no external filtering or buffering is required, tie this pin directly to the mux out pin; otherwise tie the input of the conditioning network to the mux out pin. 12 sdi serial data input bus. this in put provides the data written to the on - chip control registers. data clocks into the registers on the falling edge of the sclk input. provide data most significant bits (msb) first. 13 sdo serial data output bus. the conversion output data is supplied to this pin as a serial data stream. the bits are clocked out on the falling edge of the sclk input, and 13 sclk cycles are required to access the data. the data is provided msb first. 14 sclk serial clock. this pin acts as the serial clock input. 15 convst convert start input signal. edge triggered logic input. the falling edge of convst places the track - and - hold mode into hold mode and initiates a conversion. 16 v drive logic power supply input. the voltage supplied at this pin determines at what voltage the interface operates. connect decoupling capacitors between v drive and gnd. t he t ypical recommended values are 10 f and 0.1 f. the voltage range on this pin is 1.8 v to 5.25 v and may be different from the voltage range at v dd but must never exceed it by more than 0.3 v. 1 2 3 4 5 6 7 8 16 15 14 13 12 1 1 10 9 ad7091r-2 t o p view (not to scale) reset v dd regcap mux out gnd cs v in 0 convst sclk sdo adc in gnd sdi v in 1 v drive ref in /ref out 10891-007 rev. 0 | page 8 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 figure 6. 4- channel pin configuration table 6 . 4 - channel pin function descriptions pin no. mnemonic description 1 cs chip select input. when cs is held low, the serial bus enables and cs frames the output data on the spi. 2 reset reset. logic input. 3 v dd power supply input. the v dd range is from 2.7 v to 5.25 v. decouple this supply pin to gnd. 4 regcap decoupling capacitor pin for voltage output from internal regulator. decouple this output pin separately to gnd using a 2.2 f capacitor. 5 ref in /ref out voltage reference output, 2.5 v. decouple this pin to gnd. t he t ypical recommended decoupling capacitor value is 2.2 f. the user can either access the internal 2.5 v reference or overdrive the internal reference with the voltage applied to this pin. the reference voltage r ange for an externally applied reference is 1.0 v to v dd . 6, 15 gnd chip ground. these pins are the ground reference point for all circuitry on the ad7091r - 4 . 7 mux out multiplexer output. the output of the multiplexer appears at this pin. if no external filtering or buffering is required, tie this pin directly to the adc in pin; otherwise, tie the output of the conditioning network to the adc in pin. 8 v in 0 analog input 0 . single - ended analog input. the analog input range is 0 v to v ref . 9 v in 2 analog input 2. single - ended analog input. the analog input range is 0 v to v ref . 10 alert/busy/gpo 0 alert output (alert). this is a multifunction pin determined by the configu ration register. when functioning as alert, this pin is a logic output indicating that a conversion result has fallen outside the limit of the register settings. busy output (busy). when the alert/busy / gpo 0 pin is configured as a busy output, use this pin to indicate when a conversion is taking place. general - purpose digital output ( gpo0 ). the pin can also function as a general - purpose digital output. 11 gpo 1 general - purpose digital output. 12 v in 3 analog input 3. single - ended analog input. the analog input range is 0 v to v ref . 13 v in 1 analog input 1. single - ended analog input. the analog input range is 0 v to v ref . 14 adc in adc input. this pin allows access to the on - chip track - and - hold. if no external filtering or buffering is required, tie this pin directly to the mux out pin; otherwise, tie the input of the conditioning network to the mux out pin. 16 sdi serial data input bus. this i nput provides data written to the on - chip control registers. data clocks into the registers on the falling edge of the sclk input. provide data msb first. 17 sdo serial data output bus. the conversion output data is supplied to this pin as a serial data stream. the bits are clocked out on the falling edge of the sclk input, and 13 sclk cycle s are required to access the data. the data is provided msb first. 18 sclk serial clock. this pin acts as the serial clock input. 19 convst convert start input signal. edge triggered logic input. the falling edge of convst places the track - and - hold mode into hold mode and initiates a conversion. 20 v drive logic power supply input. the voltage supplied at this pin determines at what voltage the interface operates. connect decoupling capacitors between v drive and gnd. t he t ypical recommended values are 10 f and 0.1 f. the voltage range on this pin is 1.8 v to 5.25 v and may be different from the voltage range at v dd but must never exceed it by more than 0.3 v. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 1 1 ad7091r-4 t o p view (not to scale) reset v dd regcap mux out gnd cs v in 0 v in 2 alert/busy/gpo 0 convst sclk sdo adc in gnd sdi v in 1 v in 3 gpo 1 v drive ref in /ref out 10891-005 rev. 0 | page 9 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet figure 7. 8 - channel pin configuration table 7 . 8 - channel pin function descriptions pin no. mnemonic description 1 cs chip select input. when cs is held low, the serial bus enables and cs frames the output data on the spi. 2 reset reset. logic input. 3 v dd power supply input. the v dd range is from 2.7 v to 5.25 v. decouple this supply pin to gnd . 4 regcap decoupling capacitor pin for voltage output from internal regulator. decouple this output pin separately to gnd using a 2.2 f capacitor. 5 ref in /ref out voltage reference output , 2.5 v. decouple this pin to gnd. t he t ypical recommended decoupling capacitor value is 2.2 f. the user can either access the internal 2.5 v reference or overdrive the internal reference with the voltage applied to this pin. the reference voltage range f or an externally applied reference is 1.0 v to v dd . 6, 19 gnd chip ground. these pins are the ground reference point for all circuitry on the ad7091r -8 . 7 mux out multiplexer output. the output of the multiplexer appears at this pin. if no external filtering or buffering is required, tie this pin directly to the adc in pin; otherwise, tie the output of the conditioning network to the adc in pin. 8 v in 0 analog input 0 . single - ended analog input. the analog input range is 0 v to v ref . 9 v in 2 analog input 2. single - ended analog input. the analog input range is 0 v to v ref . 10 alert/busy/gpo 0 alert output (alert). this is a multifunction pin determined by the configuration register. when functioning as alert, this pin is a logic output indicating that a conversion result has fallen outside the limit of the register settings. busy output (bu sy). when the alert/busy / gpo 0 pin is configured as a busy output, use this pin to indicate when a conversion is taking place. general - purpose digital output ( gpo0 ). the pin can also function as a general - purpose digital output. 11 v in 4 analog input 4. single - ended analog input. the analog input range is 0 v to v ref . 12 v in 6 analog input 6. single - ended analog input. the analog input range is 0 v to v ref . 13 v in 7 analog input 7. single - ended analog input. the analog input range is 0 v to v ref . 14 v in 5 analog input 5. single - ended analog input. the analog input range is 0 v to v ref . 15 gpo 1 general - purpose digital output. 16 v in 3 analog input 3. single - ended analog input. the analog input range is 0 v to v ref . 17 v in 1 analog input 1. singl e - ended analog input. the analog input range is 0 v to v ref . 18 adc in adc input. this pin allows access to the on - chip track - and - hold. if no external filtering or buffering is required, tie this pin directly to the mux out pin; otherwise, tie the input of the conditioning network to the mux out pin. 20 sdi serial data input bus. data to be written to the on - chip control registers is provided on this input. data is clocked into the registers on the falling edge of the sclk i nput. provide data msb first. 21 sdo serial data output bus. the conversion output data is supplied to this pin as a serial data stream. the bits are clocked out on the falling edge of the sclk input, and 13 sclk cycles are required to access the data. th e data is provided msb first. 22 sclk serial clock. this pin acts as the serial clock input. 23 convst convert start input signal. edge triggered logic input. the falling edge of convst places the track - and - hold mode into hold mode and initiates a conversion. 1 2 3 4 5 6 7 8 9 10 12 1 1 reset v dd regcap mux out gnd cs v in 0 v in 2 v in 6 v in 4 alert/busy/gpo 0 20 21 22 23 24 19 18 17 16 15 14 13 convst sclk sdo adc in gnd sdi v in 1 v in 3 v in 7 v in 5 gpo 1 v drive ad7091r-8 t op view (not to scale) ref in /ref out 10891-003 rev. 0 | page 10 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 pin no. mnemonic description 24 v drive logic power supply input. the voltage supplied at this pin determines at what voltage the interface operates. connect decoupling capacitors between v drive and gnd. t he t ypical recommended values are 10 f and 0.1 f. the voltage range on this pin is 1.8 v to 5.25 v and may be different from the voltage range at v dd but must never exceed it by more than 0.3 v. rev. 0 | page 11 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet typical performance characteristics figure 8. i ntegral nonlinearity vs. code figure 9 . histogram of a dc input at code center figure 10 . 1 0 khz fft, v dd = 3.0 v , v ref = 2.5 v external figure 11 . differential nonlinearity vs. code figure 12 . histogram of a dc input at code transition figure 13 . 1 0 khz fft, v dd = 3.0 v , v ref = 2.5 v internal 0.8 0 ?1.0 0 10891-115 inl (lsb) code 500 1000 1500 2000 2500 1.0 3000 3500 0.6 0.4 0.2 ?0.2 ?0.4 ?0.6 ?0.8 4000 4500 v dd = 3.0v v ref = 2.5v t a = 25c f sample = 1msps positive inl = +0.74lsb negative inl = ?0.37lsb 50000 10891-119 number of occurrences code 2047 60000 2048 40000 30000 20000 10000 0 2049 v dd = v drive = 3.0v 65k samples t a = 25c ?20 0 10891-117 snr (db) frequency (khz) 50 100 150 200 250 0 300 350 ?40 ?60 ?80 ?100 ?120 ?140 ?160 400 450 500 v dd = 3.0v v ref = 2.5v external t a = 25c f sample = 1msps f in = 10khz snr = 69.52db sinad = 69.21db thd = ?84.25db sfdr = ?85.79db 0.8 0 ?1.0 0 10891-116 dnl (lsb) code 500 1000 1500 2000 2500 1.0 3000 3500 0.6 0.4 0.2 ?0.2 ?0.4 ?0.6 ?0.8 4000 4500 v dd = 3.0v v ref = 2.5v t a = 25c f sample = 1msps positive dnl = +0.48lsb negative dnl = ?0.50lsb 25000 10891-120 number of occurrences code 2044 40000 2045 20000 15000 10000 5000 0 2046 2047 30000 35000 v dd = v drive = 3.0v 65k samples t a = 25c ?20 0 10891-118 snr (db) frequency (khz) 50 100 150 200 250 0 300 350 ?40 ?60 ?80 ?100 ?120 ?140 ?160 400 450 500 v dd = 3.0v v ref = 2.5v internal t a = 25c f sample = 1msps f in = 10khz snr = 69.44db sinad = 69.19db thd = ?84.21db sfdr = ?85.82db rev. 0 | page 12 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 figure 14 . snr vs. analog input frequency for various supply voltages figure 15 . sinad vs. analog input frequency for various supply voltages figure 16 . snr, sinad, and enob vs. reference voltage figure 17 . thd vs. analog input frequency for various supply voltages figure 18 . snr vs. input level figure 19 . thd and sfdr vs. reference voltage 60 62 64 66 68 70 72 1 10 100 snr (db) input frequency (khz) 2.7v 3.0v 5.0v 10891-108 t a = 25c f sample = 1msps v ref = 2.5v 60 62 64 66 68 70 72 1 10 100 sinad (db) input frequency (khz) 2.7v 3.0v 5.0v 10891-111 t a = 25c f sample = 1msps v ref = 2.5v 68.0 10891-121 snr, sinad (db) reference voltage (v) 1.0 72.0 1.5 67.0 66.0 65.0 64.0 69.0 71.0 2.5 4.0 4.5 5.0 12.00 11.80 11.60 11.40 11.20 11.00 10.80 10.60 10.40 10.20 enob (bits) 2.0 3.0 3.5 70.0 v dd = 5.0v t a = 25c f sample = 1msps f in = 10khz enob sinad snr ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 10 100 thd (db) input frequency (khz) 2.7v 3.0v 5.0v 10891-109 t a = 25c f sample = 1msps v ref = 2.5v 69.5 ?10 10891-123 snr (db) input level (db) ?9 ?8 ?7 ?6 ?5 69.6 ?4 ?2 69.4 69.3 69.2 69.1 69.0 68.9 ?1 0 ?3 v dd = 5.0v t a = 25c f sample = 1msps f in = 10khz 10891-128 thd, sfdr (db) reference voltage (v) 1.0 ?78 2.0 ?86 ?88 ?90 2.5 5.0 ?84 ?80 3.5 4.0 1.5 3.0 4.5 v dd = 5.0v t a = 25c f sample = 1msps f in = 10khz ?82 sfdr thd rev. 0 | page 13 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet figure 20 . thd vs. temperature figure 21 . snr vs. temperature figure 22 . operating current vs. throughput figure 23 . operational i dd supply current vs. temperature for various v dd supply voltages figure 24 . operational i drive supply current vs. temperature for various v drive supply voltages figure 25 . total power - down current vs. temperature for various supplies ?81 ?85 ?90 ?55 10891-129 thd (db) temperature (c) ?35 ?15 5 25 45 ?80 65 85 ?82 ?83 ?84 ?86 ?87 ?88 ?89 105 125 v dd = 5.0v f sample = 1msps f in = 10khz 70.6 ?55 10891-122 snr (db) temperature (c) ?35 ?15 5 25 45 70.8 65 85 70.4 70.2 70.0 69.6 69.4 69.2 69.0 105 125 69.8 v dd = 3.0v v ref = 2.5v f sample = 1msps f in = 10khz 450 250 0 100 10891-137 current ( a) throughput (ksps) 200 300 400 500 600 500 700 800 400 350 300 200 150 100 50 900 1000 i drive ( a) at v dd = v drive = 3.00v i dd ( a) at v dd = v drive = 3.00v i drive ( a) at v dd = v drive = 5.00v i dd ( a) at v dd = v drive = 5.00v 450 10891-125 current ( a) temperature (c) ?40 600 25 400 350 300 250 200 85 125 500 550 3.3v 5.0v 5.25v 2.7v f sample = 1msps 50 10891-126 current ( a) temperature (c) ?40 25 40 30 20 10 0 85 125 60 70 3.3v 5.0v 5.25v 2.7v 5 10891-127 total current ( a) temperature (c) ?40 8 25 4 3 2 1 0 85 125 6 7 3.3v 5.0v 5.25v 2.7v rev. 0 | page 14 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 figure 26 . t dsdo delay vs. sdo capacitance load and supply figure 27 . offset error vs. temperature figure 28 . offset error match vs. temperature figure 29 . psrr vs. ripple frequency figure 30 . gain error vs. temperature figure 31 . gain error match vs. temperature 0 2 4 6 8 10 12 10 20 30 40 50 t dsdo del a y (ns) sdo ca p aci t ance load (pf) v dr i ve = 3 v , ?40c v dri ve = 3 v , +25c v dr i ve = 3 v , +125c v dr i ve = 1 . 8 v , +125c v dr i ve = 1 . 8 v , +25c v dr i ve = 1 . 8 v , ?40c 10891-113 1.0 ?55 10891-130 offset error (mv) temperature (c) ?35 ?15 5 25 1.5 45 85 0.5 0 ?0.5 ?1.0 ?1.5 105 125 65 ch 2 ch 1 ch 0 ch 3 ch 6 ch 5 ch 4 ch 7 ?55 10891-131 offset error match (mv) temperature (c) ?35 ?15 5 25 1.5 45 85 1.0 0 ?0.5 ?1.0 ?1.5 105 125 65 0.5 70 75 80 85 90 95 100 1 10 100 1000 psrr (db) ripple frequency (khz) 10891-136 t a = 25c v ref = 2.5v externa l f sample = 1 m s p s v dd = v drive = 3.00v v dd = v drive = 5.00v 0.08 0 ?0.10 ?55 10891-133 gain error (%fs) temperature (c) ?35 ?15 5 25 45 0.10 65 85 0.06 0.04 0.02 ?0.02 ?0.04 ?0.06 ?0.08 105 125 ch 2 ch 1 ch 0 ch 3 ch 6 ch 5 ch 4 ch 7 0.08 0 ?0.10 ?55 10891-134 gain error match (%fs) temperature (c) ?35 ?15 5 25 45 0.10 65 85 0.06 0.04 0.02 ?0.02 ?0.04 ?0.06 ?0.08 105 125 rev. 0 | page 15 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet figure 32 . channel - to - channel isolation vs. input frequency figure 33 . channel - to - channel isolation vs. temperature figure 34 . reference voltage output (v ref ) vs. current load for various temperatures figure 35 . thd vs. source impedance figure 36 . internal reference vs. temperature ?70 1 10891-124 channel-to-channel isolation (db) input frequency (khz) 10 ?60 ?80 ?90 ?100 ?110 ?120 100 v dd = 5.0v t a = 25c f sample = 1msps ?87 ?95 ?105 ?55 10891-132 channel-to-channel isolation (db) temperature (c) ?35 ?15 5 25 45 ?85 65 85 ?89 ?91 ?93 ?97 ?99 ?101 ?103 105 125 v dd = 5.0v f sample = 1msps f in = 10khz 2.484 2.486 2.488 2.490 2.492 2.494 2.496 2.498 2.500 2.502 0 20 40 60 80 100 v ref (v) current load (a) +25c ?40c +85c +125c v dd = v drive = 3v 10891- 1 14 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 10 100 1k 10k thd (db) source impedance () t a = 25c v dd = 3v f i n = 10 k h z f sample = 1 m s p s 10891-110 2.500 2.490 ?55 10891-135 internal reference voltage (v) temperature (c) ?35 ?15 5 25 45 2.510 65 85 2.505 2.495 105 125 rev. 0 | page 16 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 terminology integral nonlinearity (inl) inl is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. for the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 , the endpoints of the transfer function are zero scale, a point ? lsb below the first code transition , and full scale, a point ? lsb above the last code transition. differential nonlinearity (dnl) dnl is the difference between the measured and the ideal 1 lsb change bet ween any two adjacent codes in the adc. offset error th e offset error is the deviation of the first code transition ( 00 000 to 00 001) from the ideal (such as gnd + 0.5 lsb). offset error match this is the difference in offset error between any two in put channels. gain error for the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 , th e gain error is the deviation of the last code transition (111 110 to 111 111) from the ideal (such as v ref ? 1.5 lsb) after the offset error has been adjusted out. gain error match gain error match is the difference in gain error between any two input channels . transient response time the tra ck - and - hold amplifier returns to track mode after the end of conversion. t he t rack - and - hold acquisition time is the time required for the output of the track - and - hold amplifier to reach its final value, within 0.5 lsb, after the end of conversion . see the serial interface section for more details. signal -to - (noise + distortion) (sinad) ratio sinad is the measured ratio of signal - to - (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process ; the more levels, the smaller the quantization noise. the theore tical signal - to - (noise + distortion) ratio for an ideal n - bit converter with a sine wave input is given by signal - to - (noise + distortion) = ( 6.02 n + 1.76 ) db thus, for a 12 - bit converter, the sinad ratio is 74 db . channel -to - channel isolation channel - to - channel isolation is a measure of the level of crosstalk between the selected channel and all of the other channels. it is measured by applying a full - scale, 10 khz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel that has a dc signal applied to it. figure 32 shows the worst case across all channels for the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 . total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental . for the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 , it is defined as ( ) v v v v v v thd + + + + = v 1 is the rms amplitude of the fundamental . v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurio us noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum ; however, for adcs where the harmonics are buried in the noise floor, it is a noise peak. rev. 0 | page 17 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet theory of operation circuit information the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 are a 12 - bit, fast ( 1 msps ) , ultralow power , single - supply adc s . the devic e s o perate from a 2.7 v to 5.25 v supply. the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 are capable of throughput rates of 1 msps. the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 provide an on - chip, track - and - hold adc and a serial interface housed in a 16- lead , 20- lead, or 24 - lead tssop package, which offer s considerable space - saving advantages over alternative solutions. the serial clock input accesses data from the device . the clock for the successive approximation adc is generated i nternally. the reference voltage for the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 is provided externally , or it is generated internally by an accurate on - chip reference source. the analog input range for the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 is 0 v to v ref . the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 also feature a power - down option to save power between conversions. the power - down feature is implemented across the standard serial interface as described in the modes of operation section. converter operation the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 are successive approximation adc s based on a charge redistribution digital - to - analog converter ( dac ) . figure 37 and figure 38 show simplified schematics of the adc. figure 3 7 shows the adc during its acquisition phase. when sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on v in . figure 37 . adc acquisition phase figure 38 . adc conversion phase when the adc starts a conversion, sw2 opens and sw1 moves to position b, causing the comparator to become unbalanced (see figure 38 ) . us i ng t he control logic , the charge redistribution dac adds and subtract s fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the sar decisions are made , the comparator inputs are rebalance d . from these sar decisions, t he control logic generates the adc output code . adc transfer functio n the output coding of the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 is straight binary. the designed code transitions o ccur midway between successive integer lsb values, such as ? lsb, 1? lsb, and so on. the lsb size for the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 is v ref /4096. the ideal transfer characteristic for the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 is shown in figure 39. figure 39 . ad7091r - 2 / ad7091r - 4 / ad7091r - 8 transfer characteristic reference the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 can operate with either the internal 2.5 v on - chip reference or an externally applied reference. the logic state of the p_down lsb bit in the configuration register determines whether the internal reference is used. the internal reference is selected for the a dcs when the p_down lsb bit are set to 1. when the p_down lsb bit is set to 0, supply a n external reference in the range of 2.5 v to v dd through the ref in /ref out pin. at power - up, the internal reference disable s by default. the internal reference circuitry consists of a 2.5 v band gap r eference and a reference buffer. when operating the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 in internal reference mode, the 2.5 v internal reference is available at the ref in /ref out pin, which is typically decoupled to gnd using a 2.2 f capacitor. it is recommended to buffer the internal reference before applying it elsewhere in the system. the reference buffer requires 50 ms to power up and charge the 2.2 f decoupling capacitor during the power - up time. control logic comparator sw2 sampling capacitor acquisition phase sw1 a b agnd 10891-015 charge dac redistribution v in v dd /2 control logic comparator sw2 sampling capacitor conversion phase sw1 a b agnd 10891-016 charge dac redistribution v in v dd /2 000...000 0v adc code analog input 111...111 000...001 000...010 111...110 111...000 011...111 1lsb +v ref ? 1lsb 1lsb = v ref /4096 10891-017 rev. 0 | page 18 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 typical connection d iagr am figure 41 shows a typical connection diagram for the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 . connect a positive power supply in the 2.7 v to 5.25 v range to the v dd pin . t ypical values for these decoupling capacitors are 100 nf and 10 f. place t hese capacitors near the device pins. take care to decouple t he ref in / ref out pin to achieve specified performance. t he t ypical value for the ref in / ref out capacitor is 2.2 f , which provides an analog input range of 0 v to v ref . t he t ypical value for the regulator bypass (regcap) decoupling capacitor is 1 f. the voltage applied to the v drive input controls the voltage of the serial interface ; therefore , connect this pin to the supply voltage of the microprocessor. set v drive in the 1. 8 v to 5.25 v range . typical values for the v drive decoupling capacitors are 100 nf and 10 f. the conversion result is output in a 16 - bit word with the most significant bits (msbs) first. when an external ly applied reference is required , disable the internal reference using the configuration register . choose the e xternally applied reference voltage in the 1.0 v to 5.25 v v dd range and connect it to the ref in / ref out pin. for applications where power consumption is a concern, use the power - down mode of the adc to improve power performance. see the modes of operation section for additio nal details . analog input figure 40 shows an equivalent circuit of the analog input structure of the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 . the two diodes, d1 and d2, provide esd protection for the analog input. take care to ensure that the analog input signal never exceeds the supply rails by more than 300 mv because t his causes these diodes to become forward - biased and sta rt conducting current into the substrate. these diodes can conduct a maximum of 10 ma without causing irreversible damage to the device . figure 40 . equivalent analog input circuit the c1 capacitor in figur e 40 is typically about 400 ff and can primarily be attributed to pin capacitance. the r1 r esistor is a lumped component composed of the on resistance of a switch. this resistor is typically about 500 . the c2 c apacitor is the adc sampling capacitor and typically has a capacitance of 3. 6 pf in applications where harmonic distortion and signal - to - noise ratio are critical, drive the analog inputs from low impedance sources. large source impedances significantly affect the ac performance of the adc that can necessitate using input buffer amplifiers , as shown in figure 41 . the choice of the op amp is a function of the particular application. when no amplifiers are used to drive the analog input, limit the source impedance to low values. the maximum source impedance depends on the amo unt of thd that can be tolerated. the thd increases as the source impedance increases and performance degrades. u se an external filter on the analog input signal paths to the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 v in x pins to achieve the specified performance. this filter can be a one - pole low - pass rc filter, or similar. connect t he mu x out pin directly to the adc in pin. insert a buffer amplifier in the path , if desired. when sequencing channels, d o not place a f ilter b etween mux out and the input to any buffering because do ing so lead s to crosstalk . if buffering is not employed, do not place a filter between mux out and adc in when sequencing channels because doing so leads to crosstalk . d1 d2 r1 c2 3.6pf c1 400ff conversion phase?switch open track phase?switch closed d3 10891-019 v in v dd v ref rev. 0 | page 19 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet figure 41 . typical connection diagram with optional buffer figure 42 . typical connection diagram w ithout optional buffer ad7091r-2/ ad7091r-4/ ad7091r-8 sclk sdo microcontroller/ microprocessor/ dsp cs v in 0 gnd v dd 10f 100nf 10f 100nf regcap 1f convst 2.2f analog input 47k with busy indication v drive v drive ref in / ref out analog input sdi alert 1 v in x optional buffer adc in mux out 10891-018 560pf 33 notes 1 this pin is for the ad7091r-4/ad7091r-8. ad7091r-2/ ad7091r-4/ ad7091r-8 sclk sdo microcontroller/ microprocessor/ dsp cs v in 0 gnd v dd 10f 100nf 10f 100nf regcap 1f convst 2.2f analog input 33 560pf 47k with busy indication v drive v drive ref in / ref out analog input 33 560pf sdi alert 1 v in x adc in mux out 10891-140 notes 1 this pin is for the ad7091r-4/ad7091r-8. rev. 0 | page 20 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 registers the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 ha ve user programmable registers. table 8 contains the complete list of regis ters. the registers are either read / write (r / w) or read only (r). data is written to or read back from the read / write registers. read only registers is only read. any write to a read only register or unimplemented register address is considered no operatio n ( nop ) . a nop command is an spi command that is ignored by the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 . after a write to a read only register , the output on the subsequent spi frame is all zeros if there was no conversion before the next spi frame. similarly, any read of an unimplemented register output s zeros. addressing registers a serial transfer on the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 consists of 16 sclk cycles. the six msbs on the sdi line during the 16 sclk transfer are decoded to determine which register is addressed. the six msbs consist of the register address (addx), b its[4:0] and the read/write bit. the register address bits determine which of the on - chip registers are selected. the read/write bit determines if the data on the sdi line following the read/write bit loads into the addressed register. if the read/write bit is 1, the bits load into the register addressed by the register select bits. data load s into the register on the rising edge of cs . if the read/write bit is 0, the command is seen as a read reque st. the requested register data is available on the subsequent message on the sdo line. table 8 . register description access address register name default ad7091r - 8 ad7091r - 4 ad7091r - 2 0x00 conversion result 0x0000 r r r 0x01 channel 0x0000 r/w r/w r/w 0x02 configuration 0x00c0 r/w r/w r/w 0x03 alert i ndication 0x0000 r r r 0x04 channel 0 low limit 0x0000 r/w r/w r/w 0x05 channel 0 high limit 0x01ff r/w r/w r/w 0x06 channel 0 hysteresis 0x01ff r/w r/w r/w 0x07 channel 1 low limit 0x0000 r/w r/w r/w 0x08 channel 1 high limit 0x01ff r/w r/w r/w 0x09 channel 1 hysteresis 0x01ff r/w r/w r/w 0x0a channel 2 low limit 0x0000 r/w r/w nop 0x0b channel 2 high limit 0x01ff r/w r/w nop 0x0c channel 2 hysteresis 0x01ff r/w r/w nop 0x0d channel 3 low limit 0x0000 r/w r/w nop 0x0e channel 3 high limit 0x01ff r/w r/w nop 0x0f channel 3 hysteresis 0x01ff r/w r/w nop 0x10 channel 4 low limit 0x0000 r/w nop nop 0x11 channel 4 high limit 0x01ff r/w nop nop 0x12 channel 4 hysteresis 0x01ff r/w nop nop 0x13 channel 5 low limit 0x0000 r/w nop nop 0x14 channel 5 high limit 0x01ff r/w nop nop 0x15 channel 5 hysteresis 0x01ff r/w nop nop 0x16 channel 6 low limit 0x0000 r/w nop nop 0x17 channel 6 high limit 0x01ff r/w nop nop 0x18 channel 6 hysteresis 0x01ff r/w nop nop 0x19 channel 7 low limit 0x0000 r/w nop nop 0x1a channel 7 high limit 0x01ff r/w nop nop 0x1b channel 7 hysteresis 0x01ff r/w nop nop 0x1c reserved 0x0000 nop nop nop 0x1f reserved 0x0000 nop nop nop rev. 0 | page 21 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet conversion result re gister the conversion result register is a 16 - bit read only register that stores the result s from the most recent adc conversion in straight binary format. the channel id of the converted channel and the alert status are also included in the register . figure 43 . conversion result register tale 9 . conversion result register map msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ch_id alert conv_result table 10 . bit descriptions for the conversion result register bit(s) name description reset access [15:13] ch_id 3 - bit c hannel id of channel converted 0x0 r b15 1 , 2 b14 2 b13 analog input channel 0 0 0 v in 0 0 0 1 v in 1 0 1 0 v in 2 0 1 1 v in 3 1 0 0 v in 4 1 0 1 v in 5 1 1 0 v in 6 1 1 1 v in 7 12 alert a lert flag 0 r 0 : no alert occurred 1 : alert occurred [11:0] conv_result 12 - bit c onversion result 0x000 r 1 always zero on the ad7091r - 4 . 2 always zero on the ad7091r - 2 . rev. 0 | page 22 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 channel register the channel register on the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 is an 8 - bit, read/write register. each of the eight analog input channels has one corresponding bit in the channel register. to select a channel for inclusion in the channel conversion sequence , set the corresponding channel bit to 1 in t he channel register. there is a latency of one conversion before the channel conversion sequence is updated. if the channel register is programmed with a new value, the conversion sequence is reset to the lowest numbered channel in the new value. figure 44 . channel registers tale 11 . channel register map msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 reserved ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 table 12 . bit descriptions for the channel register bit(s) name description reset access [15:8] reserved reserved 0x00 r 7 ch7 convert on channel 7 0x0 r/w 0: disable channel 7 1: enable channel 7 6 ch6 convert on channel 6 0x0 r/w 0: disable channel 6 1: enable channel 6 5 ch5 convert on channel 5 0x0 r/w 0: disable channel 5 1: enable channel 5 4 ch4 convert on channel 4 0x0 r/w 0: disable channel 4 1: enable channel 4 3 ch3 convert on channel 3 0x0 r/w 0: disable channel 3 1: enable channel 3 2 ch2 convert on channel 2 0x0 r/w 0: disable channel 2 1: enable channel 2 1 ch1 convert on channel 1 0x0 r / w 0: disable channel 1 1: enable channel 1 rev. 0 | page 23 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet bit(s) name description reset access 0 ch0 convert on channel 0 0x0 r / w 0: disable channel 0 1: enable channel 0 configuration regist er the configuration register is a 16 - bit, read/ write register that is used to set the operating mode s of the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 . figure 45 . configuration register tale 13 . configuration register map msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 reserved srst reserved alert_ sticky alert_ drive_type busy alert_en_ or_gpo0 alert_pol_ or_gpo0 gpo1 p_down table 14 . bit descriptions for the configuration register bit(s) name description reset access [15:10] r eserved 0x00 r 9 srst software r eset bit. setting this bit resets the internal digital control logic and the result and alert registers, but it does not reset the other m emory map registers. this bit automatically clear s in the next clock cycle. note that it l oads random access memory ( ram ) from fuses. 0x0 rwac 0: s oft reset not active. 1: activate soft reset . 8 reserved 0x0 r 7 alert_sticky alert _sticky bit is sticky. it is not cleared on a valid hysteresis condition. 0x1 r / w 0: clear alert 1 if the result falls beyond hysteresis . 1: clear alert 1 only on a read or soft reset . rev. 0 | page 24 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 bit(s) name description reset access 6 alert_drive_type drive type of alert 1 pin. 0x1 r / w 0: alert 1 pin is of open - drain drive type. 1: alert 1 pin is of cmos drive type. 5 busy alert 1 pin indicates if the part is busy converting. 0x0 r / w 0: alert 1 pin is not used for busy status. 1: alert 1 pin is used for busy status, provided alert_en _or_gpo 0 ) is 1. else, this bit is always read back as 0. 4 alert_en_or_gpo0 enable alert pin or gpo 0 1 . 0x0 r / w 0: alert 1 pin used as gpo 0 1 . 1: alert 1 pin is used for alert 1 /busy 1 status. 3 alert_pol_or_gpo0 polarity of alert 1 pin (if alert_en _or_gpo 0 is 1) or value at gpo 0 1 . 0x0 r / w 0: active low alert 1 polarity (if alert_en _or_gpo 0 = 1) or gpo 0 1 = 0. 1: active high alert 1 polarity (if alert_en _or_gpo 0 = 1) or gpo 0 1 = 1. 2 gpo1 value at gpo 1 1 . 0x0 r / w 0: drive 0 on gpo 1 1 pin. 1: drive 1 on gpo 1 1 pin. [1:0] p_down power -d own mode. 0x0 r / w setting mode sleep mode/bias generator internal reference 00 mode 0 off off 01 mode 1 off on 10 mode 2 on off 11 mode 2 on on 1 when referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is releva nt to the specification is listed. for full pin names of multifunction pins, refer to the pin configurations and function descriptions section. rev. 0 | page 25 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet alert indication register the 16 - bit alert indication register is a read only register that provides information on an alert event. if a conversion result activates the alert function of the alert/busy/gpo 0 pin, as described in the channel x low limit register section and the channel x high limit register section, the alert register can be read to determine the source of the alert. the register contains two status bits per channel, one corresponding to the high limit , and the other to the low limit. the bit with a status equal to 1 shows where the violation occurred , that is, on which channel , and whether the violation occurred on the upper or lower limit. if a second alert event occurs on another channel between receiving the first alert and i nterrogating the alert register, the corresponding bit for that alert event is also set. the contents of the alert indication register are reset by reading it. the alert indication register is reset on the second sclk cycle of the spi frame where the aler t data is read out. if a conversion happens in the meantime, the conversion result is sent instead of the alert indication register contents. the alert indication register is not reset in this case. the alert bits for any unimplemented channels on the two and four channel devices always return zeros. figure 46 . alert indication register (figure shows default register value of 0, indicating no alert has occurred) tale 15. alert indication register register map tale 16 . bit descriptions for the alert indication register bit(s) bit name description reset access 15 lo_7 channel 7 low alert status 0x0 r 0: no alert on channel 7 1: low alert occurred on channel 7 14 hi_7 channel 7 high alert status 0x0 r 0: no alert on channel 7 1: high alert occurred on channel 7 msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 lo_7 hi_7 lo_6 hi_6 lo_5 hi_5 lo_4 hi_4 lo_3 hi_3 lo_2 hi_2 lo_1 hi_1 lo_0 hi_0 rev. 0 | page 26 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 bit(s) bit name description reset access 13 lo_6 channel 6 low alert status 0x0 r 0: no alert on channel 6 1: low alert occurred on channel 6 12 hi_6 channel 6 high alert status 0x0 r 0: no alert on channel 6 1: high alert occurred on channel 6 11 lo_5 channel 5 low alert status 0x0 r 0: no alert on channel 5 1: low alert occurred on channel 5 10 hi_5 channel 5 high alert status 0x0 r 0: no alert on channel 5 1: high alert occurred on channel 5 9 lo_4 channel 4 low alert status 0x0 r 0: no alert on channel 4 1: low alert occurred on channel 4 8 hi_4 channel 4 high alert status 0x0 r 0: no alert on channel 4 1: high alert occurred on channel 4 7 lo_3 channel 3 low alert status 0x0 r 0: no alert on channel 3 1: low alert occurred on channel 3 6 hi_3 channel 3 high alert status 0x0 r 0: no alert on channel 3 1: high alert occurred on channel 3 5 lo_2 channel 2 low alert status 0x0 r 0: no alert on channel 2 1: low alert occurred on channel 2 4 hi_2 channel 2 high alert status 0x0 r 0: no alert on channel 2 1: high alert occurred on channel 2 3 lo_1 channel 1 low alert status 0x0 r 0: no alert on channel 1 1: low alert occurred on channel 1 2 hi_1 channel 1 high alert status 0x0 r 0: no alert on channel 1 1: high alert occurred on channel 1 1 lo_0 channel 0 low alert status 0x0 r 0: no alert on channel 0 1: low alert occurred on channel 0 0 hi_0 channel 0 high alert status 0x0 r 0: no alert on channel 0 1: high alert occurred on channel 0 rev. 0 | page 27 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet channel x low limit register each analog input channel of the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 has its own low limit register. the low limit registers are 16 - bit read/write registers . s ee table 8 for the register addresses . the low limit registers store the lower limit of the conversion value that activates the alert output. of the 16 bits , only the nine least significant bits ( lsbs ) are used, db8 to db0. d b15 to bit db9 are not used. these nine bits , which are programmed by the user , are used as the msb s of the internal 12 - bit register. the three lsbs in the internal 12- bit registers are set to 000. channel x high limit register each analog input channel of the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 has its own high limit register. the high limit registers are 16 - bit read/write registers . s ee table 8 for the register addresses . the high limit registers store the upper limit of the conversion value that activates the alert output. of the 16 bits , only the nine lsbs are used, db8 to db0. db15 to db9 are not used. these nine bits , which are programmed by the user , are used as the most significant bits of the internal 12 - bit register. the three lsbs in the internal 12 - bit registers are set to 111. channel x hysteresis register each analog input channel of the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 has its own hysteresis register, which are 16 - bit read/write registers. see table 8 for the register addresses. the hysteresis register stores the hysteresis value ( n ) when using the limit registers. the hysteresis value determines the reset point for the alert /busy/gpo 0 pin if a violation of the limits has occurred. of the 16 bits , only the nine lsbs are used, db8 to db0. db15 to db9 are not used in the register and are set to zero s. these nine bits , which are programmed by the user , are used as the lsbs of the internal 12 - bit register. the three msbs are set to 000. table 17 . channel x low li mit register register map msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 reserved ch x lo w limit table 18 . bit descriptions for the channel x low limit register bit(s) bit name description reset access [15:9] reserved reserved 0x00 r [8:0] ch x lo w limit low limit value for channel x 0x000 r / w table 19 . channel x high limit register map msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 reserved ch x hi gh limit table 20 . bit descriptions for the channel x high limit register bits bit name description reset access [15:9] reserved 0x00 r [8:0] ch x high limit high limit value for channel x 0x1ff r / w table 21 . channel x hysteresis register map msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 reserved ch x hyst eresis table 22 . bit descriptions for the channel x hysteresis register bit(s) bit name description reset access [15:9] reserved 0x00 r [8:0] ch x hysteresis hysteresis value for channel x 0x1ff r / w rev. 0 | page 28 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 serial interface the spi is a 4 - wire interface ( three inputs and one output) for serial data communication. it has a chip - select ( cs ) line, a serial clock (sclk), a serial data input (sdi) , and a serial data output (sdo). data transfers on sdi and sdo take place with respect to sclk. cs is used to frame the data and is active low. when cs is high, sdo is kept in high impedance. the falling edge of cs takes the sdo line out of the high impedance state. a rising edge on cs returns the sdo to a high impedance state. the spi implemented on the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 can support both of the following: cpha and cpol = 0 , and cpha and cpol = 1. this support ensure s that the device can interface to micro - controllers and dsps that keep either sclk high or sclk low when cs is not asserted. the device ignores sclk toggling when cs is not asserted. reading conversion r esult the convst signal is used to initiate the conversion process. a high - to - low transition on the convst signal puts the track - and - hold into hold mode and samples the analog input at this point. a conver sion is initiated and requires 6 0 0 ns to complete . before the end of the conversion, take the convst signal high again . when the conversion process is finished, the track - and - hold mode goes back into track mode . then, take t he cs pin low and the conversion result clock s out on the sdo pin. the data is shifted out of the device as a 16 - bit word under the control of the serial clock (sclk) input. the data is shifted out on falling edge of sc lk , and the data bits are valid on both the rising edge and the falling edge. the msb is shifted out on the falling edge of cs . the final bit in the data transfer is valid on the 16th rising edge and 16th falling edge, having clocked out on the previous (15th) falling edge. after the 16th falling edge, take cs high again to return the sdo to a high impedance state. if another conversion is required, take the convst pin low again (after at least 1 s) , an d repeat the read cycle. the timing diagram for this operation is shown in figure 48. writing data to the registers all the read/write registers in the device can be written to over t he spi. a register write command is performed by a single 16 - bit spi access. the format for a write command is shown in table 23 . bits[ b 15: b 11] contain the register address . s ee table 8 for t he complete list of register addresses. setting b it b 10 to 1 selects a write command. the subsequent 10 bits (bits [ b 9: b 0] ) contain the data to be written to the selected register. readi ng data from the registers all the registers in the device can be read over the spi. a register read is performed by issuing a register read command followed by an additional spi command that can be either a valid command or nop. the format for a read comm and is shown in table 24. bits[ b 15: b 11] contain the register address . s ee table 8 for t he complete list of register addresses. setting b it b 10 to 0 selects a read command. the device ignores the subsequent bits (bits [ b 9: b 0] ) . any conversion event is treated as a special case and overrides a previous read command. the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 always drive out the conversion result register on sdo after a conversion even though a register read was initiated in the previous spi frame. table 23 . write command message configuration msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 register address[4:0] 1 data[9:0] figure 47 . serial interface register write cs sdi sdo convst write reg 1 conv result write reg 2 invalid data write reg 3 invalid data 10891-024 rev. 0 | page 29 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet table 24. read command message configuration msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 register address[4:0] 0 dont care figure 48 . serial interface register read cs sdi sdo convst read reg 1 conv res read reg 2 reg 1 data read reg 3 reg 2 data 10891-025 rev. 0 | page 30 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 modes of operation normal mode the user control s whether the device remai ns in normal mode or enters power - down mode . these modes of operation provide flexible power management options allowing optimization of the power dissipation and throughput rate ratio for different application requirements. to achieve the fastest throughput rate performance, use n ormal mode. p ower - up times are not a n issue for th e ad7091r - 2 / ad7091r - 4 / ad7091r - 8 because they remain fully powered at all times. figure 49 shows the general diagram of the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 in normal mode. the conversion initiate s on the falling edge of convst , as described in the serial interface section. to ensure that the device remains fully powered up at all times, return convst high before t convert and keep it high until the conversion has finished. the end of conversion (eoc) point shown in figure 49 indicates the end of eoc and the moment when the logic level of convst is tested. to read back data stored in the conversion result register, wait until the conversion is complete d. then, take cs low , and the conversion data clock s out on the sdo pin. the output shift regist er is 16 bit s wide. data is shifted out of the device as a 16 - bit word under the control of the serial clock (sclk) input. the full timing diagram for this operation is shown in figure 4 . when the conversion read is completed, pull convst low again to start another conversion. power - down mode when slower throughput rates and lower power consumption are req uired, use p ower - down mode by either power ing down the adc between each conversion or by perform ing a series of conversions at a high throughput rate and then power ing down the adc for a relatively long d uration between these burst conversions. when the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 are in power - down mode, all analog circuitry power down; however, the serial interface is active. to enter power - down, write to the power - down configuration bits in the configuration register , as seen in table 13 . to e nte r full power - down mode, set t he sleep mode/bias generator bit to 1 , and set the internal reference bit to 0, which ensure s that all analog circuitry and the internal reference power s down. when t he internal reference is enabled, it consume s power anytime b it 0 of the configuration register is set to 1. the serial interface of the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 is functional in power - down; therefore, user can read back result s of the conversion after the device enters power - down mode. to exit this mode of operation and power up the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 again, write to the power - down configuration bits in the configuration register (see table 13 ) . on the rising edge of convst , the device begins to power up. the power - up time of the ad7 091r - 2 / ad7091r - 4 / ad7091r - 8 is typically 1 s. after power - up is complete, the adc is fully powered up, and the input signal is properly acquired. to start the next conversion, operate the interface as described in the normal mode section. when using the int ernal reference , and the device i s in full power - down mode, the user must wait to perform conversions until the internal reference has had time to power up and settle. the reference buffer requires 50 ms to power up and charge the 2.2 f decoupling capacit or during the power - up time. by using the power - down mode on the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 when this device is not converting, the average power consumption of the adc decreases at lower throughput rates. use p ower - down mode with lower throughput rates. when t here is not a significant time interval between bursts of conversions, use normal mode (see the normal mode section) . figure 49 . serial interface read timing in normal mod e t dis t en eoc t convert t eoccsl t cnvpw conversion data notes 1. don?t care cs convst sdo 10891-026 rev. 0 | page 31 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet a lert ( ad7091r - 4 and ad7091r - 8 o nly) the alert functionality is used as an out - of - range indicator. an alert event is triggered when the value in the conversion result register exceeds the ch x hi gh lim it value in the channel high limit register or falls below the ch x lo w lim it value in the channel low limit register for a selected channel. detailed alert information is access ible in the alert register. the register contains two status bits per chann el, one corresponding to the high limit , and the other to the low limit. a logical or of alert signals for all channels creates a common alert value. this value can be accessed by the alert bit in the conversion result register and configured to drive out on the alert function of the alert/busy/gpo 0 pin . the alert/busy/gpo 0 pin is configured as alert by configuring the following bits in the configuration register: ? set the al er t_en _or_gpo0 bit , b it 4, to 1 . ? set the busy bit , b it 5, to 0 . ? set the al er t_ pol_or_ gpo 0 bit , b it 3, to 0 for the the alert function of the alert/busy/gpo 0 pin to be active low and set it to 1 for the the alert function of the alert/busy/gpo 0 pin to be active high . the alert register, alert bit , and the alert function of the alert/busy/gpo 0 pin are cleared by reading the alert register contents. additionally , i f the conversion result goes beyond the hysteresis value for a selected channel , the alert bit corresponding to that channel is reset automatically. t he automatic clearing of the alert status can be disabled by setting the al er t_st ick y bit in the configuration register to 1. if the alert_sticky bit is set when an alert occurs , it can only be reset by a read of the alert register . issuing a software rese t also clear s the alert status. the alert/busy/gpo 0 pin has an open - drain configuration that allows the alert outputs of several ad7091r - 4 / ad7091r - 8 devices to be wired together when the alert function of the alert/busy/gpo 0 pin is active low. the alert_drive_type bit (bit 6) of the configuration register controls t he alert/ busy/gpo 0 pin configuration . use t he alert_pol_or_gpo0 bit ( b it 3 ) of the configuration register to set the active polarity of the alert output. the power - up default is active low. when using the alert function of the alert/busy/gpo 0 pin and the open - drain configur ation , an extern al pull - up resistor is required . connect t he external pull - up resistor to v drive . the resistor value is application depend e nt ; however, it must be large enough to avoid excessive sink currents when the alert function of the alert/busy/gpo 0 pin is triggered . b usy ( ad7091r - 4 and ad7091r - 8 o nly) when con figuring the alert/busy / gpo 0 pin as a busy output , use the pin to indicate when a conversion is taking place. to configure t he alert/busy / gpo 0 pin as busy , use the following bits in the configuration register: ? set the alert_en_or_gpo0 bit , b it 4, to 1 . ? set the busy bit , b it 5, to 1 . ? set the alert_pol_or_gpo0 bit, bit 3, to 0 for the busy pin to be active low , and set it to 1 for the busy pin to be active high . when using the busy function of the alert/busy/gpo 0 pin pin , an external pull - up resistor is required because the output is an open - drain configuration . connect the external pull - up resistor to v drive . the resistor value is application depend e nt ; however, it must be large enough to avoid excessive sink currents at the busy function of the the alert function of the alert/busy/gp o 0 pin . rev. 0 | page 32 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 channel sequencer the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 include a channel sequencer that is useful for scanning channels in a repeated fashion. channels included in the sequence are configured in the c hannel r egister. if all the bits in the c hannel re gister are 0 , channel 0 is selected by default , and all conversions happen on this channel. if the c hannel r egister is nonzero , the conversion sequence starts from the lowest numbered channel enabled in the c hannel r egister. the sequence cycles through all the enabled channels in ascending order. after all the channels in the sequence are converted, the sequence starts again. there is a latency of one conversion before the channel conversion sequence is updated. if the channel register is programmed with a new value, the conversion sequence is reset to the lowest numbered channel in the new value. figure 50 . channel sequencer figure 51 . channel sequencer multiple channel write nop nop nop result channel 5 result channel 4 result channel 0 result channel 0 write 0x00f0 channel reg cs sdi sdo convst 10891-028 10891-029 result channel 1 result channel 0 result channel 0 result channel 0 write 0x001 channel reg cs sdi sdo convst result channel 2 write 0x002 channel reg write 0x004 channel reg write 0x008 channel reg write 0x0010 channel reg rev. 0 | page 33 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet daisy chain this mode is intended for applications where multiple ad7091r - 2 / ad7091r - 4 / ad7091r - 8 devices are used . this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. all adc slaves are addressed by the sam e cs , convst , and sclk signals. the sdi of the first ad7091r - 2 / ad7091r - 4 / ad7091r - 8 slave in the chain is driven directly by the mosi pin of the spi master. the sdo of the first slave is connected to the sdi of the second slave. all the subsequent slaves are connected in this fashion , and the sdo of the last slave drive s the master input, slave output ( miso ) pin of the master. a connection diagram example using two ad7091r - 2 / ad7091r - 4 / ad7091r - 8 devices is shown in figure 52. each ad7091r - 2 / ad7091r - 4 / ad7091r - 8 slave in the chain require s a 16 - bit spi command. if there are n slaves , each spi frame must have n 16 bits of data. in the ad7091r - 2 / ad7091r - 4 / ad7091r - 8 , when the bit counter crosses 16 bits , all of the received bits are sent out over the sdo. the output from the first slave is the input of the second slave. effectively, each slave ignores all the incoming 16 - b it spi commands , except the last one. the spi command received just before the cs rising edge is the only valid spi command for a given device in the daisy chain. the output on the next spi frame is determined by the valid spi command or any conversion event. the methods for reading a conversion result to configuring the slave registers are outlined in figure 53 to figure 57 for a two - slave example. additional slave devices can be added to the chain by following the same principles defined for the two - device configuration . figure 52 . daisy - chain configuration figure 53 . conversion in a two - slave daisy - c hain mode configuration miso sclk convert digital host spi master sdo cs ad7091r-x ss sclk sdo cs ad7091r-x convst sclk convst sdi slave b slave a sdi mosi 10891-030 1 nop nop nop nop nop nop conv_result a conv_result b conv_result a conv_result a conv_result b conv_result a 16 17 32 1 16 17 32 cs sclk sdi a convst sdo a/ sdi b sdo b 10891-031 rev. 0 | page 34 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 figure 54 . single register write in a two - slave daisy - c hain mode configuration figure 55 . single register read in a two - slave daisy - c hain mode configuration figure 56 . multiple register read in a two - slave daisy - c hain mode configuration figure 57 . multiple register write in a two - slave daisy - c hain mode configuration cs sclk sdi a convst sdo a/ sdi b sdo b 10891-032 1 16 17 32 write reg1 b write reg2 a write reg1 b invalid data invalid data invalid data 1 read reg1 b read reg2 a nop nop nop read reg1 b conv_result a conv_result b conv_result a data reg2 a data reg1 b data reg2 a 16 17 32 1 16 17 32 cs sclk sdi a convst sdo a/ sdi b sdo b 10891-033 1 16 17 32 1 16 17 32 1 16 17 32 read reg1 b read reg2 a read reg1 b conv_result a conv_result b conv_result a read reg3 b read reg4 a read reg3 b data reg2 a data reg1 b data reg2 a nop nop nop data reg4 a data reg3 b data reg4 a cs sclk sdi a convst sdo a/ sdi b sdo b 10891-034 1 16 17 32 1 16 17 32 1 16 17 32 write reg1 b write reg2 a write reg1 b conv_result a conv_result b conv_result a write reg3 b write reg4 a write reg3 b invalid data invalid data invalid data nop nop nop invalid data invalid data invalid data cs sclk sdi a convst sdo a/ sdi b sdo b 10891-035 rev. 0 | page 35 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet outline dimensions figure 58 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters figure 59 . 20 - lead thin shrink small outline package [tssop] (ru - 20) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarity 0.10 rev. 0 | page 36 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 figu re 60 . 24 - lead thi n shrink small outline package [tssop] (ru - 24) dimensions shown in millimeters ordering guide model 1 channels temperature range package description package option ad7091r - 2bruz 2 ?40c to +125c 16 - lead thin shrink small outline package [tssop] ru -16 ad7091r - 2bruz -rl7 2 ?40c to +125c 16 - lead thin shrink small outline package [tssop] ru -16 eval - ad7091r - 2 sdz evaluation board ad7091r - 4bruz 4 ?40c to +125c 20 - lead thin shrink small outline package [tssop] ru -20 ad7091r - 4bruz -rl7 4 ?40c to +125c 20 - lead thin shrink small outline package [tssop] ru -20 eval - ad7091r -4 sdz evaluation board ad7091r - 8bruz 8 ?40c to +125c 24 - lead thin shrink small outline package [tssop] ru -24 ad7091r - 8bruz -rl7 8 ?40c to +125c 24 - lead thin shrink small outline package [tssop] ru -24 eval - ad7091r -8 sdz evaluation board eval - sdp - cb1z evaluation controller board 1 z = rohs compliant part. 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad rev. 0 | page 37 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet notes rev. 0 | page 38 of 40
data sheet ad7091r- 2/ad7091r - 4/ad7091r - 8 notes rev. 0 | page 39 of 40
ad7091r- 2/ad7091r - 4/ad7091r - 8 data sheet notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10891 - 0- 12/13(0) rev. 0 | page 40 of 40

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